As a Game Boy developer, you will eventually come across the terms machine cycle (M-cycle) and time cycle (T-cycle). It seems to be widely understood that Game Boy CPU instructions take one or more M-cycles to execute, and each M-cycle is made up of 4 T-cycles (Figure 1). Unfortunately, I could not find any official Nintendo source that details the timing of Game Boy CPU instructions. Time to conduct some research …

CPU instructionMachine cycles(1 MHz)Time cycles(4 MHz)Time cycles(8 MHz)CGB double speedCPU instructionnormal CPU speedMachine cycles(2 MHz)
Figure 1: a Game Boy CPU instruction spanning 2 M-cycles (normal CPU speed and CGB double speed)

Manuals and Speculations

For as long as I can recall, the Game Boy CPU has been believed to be a simplified version of the Zilog Z80 due to their similarities. The Zilog Z80 User Manual provides in-depth timing information and depicts CPU instructions as a series of operations, such as memory reads and writes. Each operation is said to take one M-cycle to execute and each M-cycle requires 3 to 6 clock periods or T-cycles. However, the Game Boy is not known for having variable M-cycle lengths, so the Z80 User Manual may not be the best source of information in this context.

At some point, Nintendo’s Game Boy Programming Manual was available online. Unfortunately, the manual does not provide any information about the type of CPU used in the Game Boy or its instruction timing. The Overview of CPU Features chapter mentions a source oscillation of 4 MHz (8 MHz for CGB double speed) with instruction cycles of approximately 0.954 μs (0.477 μs for CGB double speed). The term “instruction cycle” apparently refers to what is commonly known as an M-cycle, but not the actual CPU Instruction Cycle. The manual does not go into further detail about instruction cycles or CPU instruction timing, let alone provide information about T-cycle timing.

In January 2019, Joonas Javanainen (also known as “Gekkio”) discovered that the Game Boy CPU is based on either a Sharp SM83 core or a compatible one. He shared a thorough analysis of his findings on nesdev. (Interestingly, the SM83 was originally designed for appliances like air conditioners and washing machines.)

The Sharp Microcomputer Databook for the SM83x mentions that one instruction cycle takes 1 microsecond for a main clock frequency of 4 MHz and 0.5 microseconds for a main clock frequency of 8 MHz. The manual also includes information about the chip’s fetch execute overlap, which is illustrated in a diagram that associates instruction cycles with system clock cycles and mentions a system clock of 1 MHz being obtained from a main clock of 4 MHz.

In summary, SM83 CPU instructions are carried out over multiple instruction cycles (M-cycles), and each instruction cycle takes 4 main clock cycles (T-cycles) to execute. This coincides with the general understanding of the timing of Game Boy CPU instructions.

CPU Instructions & M-cycles

With M-cycles and T-cycles confirmed, we can move on to the next questions:

  1. How many M-cycles are needed for each Game Boy CPU instruction?
  2. Which operation (such as reading a byte from memory) is performed during which M-cycle for each Game Boy CPU instruction?

Unfortunately, the Sharp Microcomputer Databook doesn’t provide much information on these questions. I couldn’t find any other documentation from Sharp or Nintendo either. So, we’ll have to rely on information gathered by the community.

Pan Docs is one of the most extensive technical references available for the Game Boy and contains a list of CPU instructions and the number of M-cycles they take. This information answers our first question and reveals that CPU instructions can take anywhere from 1 to 5 M-cycles to execute. It’s important to note that the Pan Docs (in that regard) are not based on any source from Sharp or Nintendo, but they have been checked and verified by the community to a degree where they are considered quite accurate.

For a more in-depth look at this topic, the Game Boy: Complete Technical Reference by Joonas Javanainen is a great resource. He has done a fantastic job of dissecting instructions into M-cycles and their related operations, taking into account the SM83’s prefetching. As of January 2023 some instructions were still missing though.

CPU instructionMachine cycleMemory readMemory addressM1OP codepreviousPCLD A, (HL+)M2AHLnext OPM3PC + 1
Figure 2: M-cycles for Game Boy CPU instruction LD A, (HL+) with OP code fetch overlap

As an example, Figure 2 depicts the M-cycles and operations performed for CPU instruction LD A, (HL+). Note that the OP code is fetched on M-cycle M1 during the execution of the previous instruction. On M-cycle M2, the value stored at the HL address is loaded into register A. Finally, on M-cycle M3, the next instruction’s OP code is fetched and HL is incremented.

Joonas Javanainen also created the Mooneye Test Suite, which tests the M-cycle timing for some CPU instructions. Other notable tests are mem-timing and mem-timing-2 created by Shay Green (known as “Blargg”).

T-cycles

The only information I was able to find on T-cycles is a chapter in Joonas Javanainen’s Game Boy: Complete Technical Reference titled “Game Boy external bus” (found in Appendix C). This chapter includes diagrams displaying the timing of data access during a read/write M-cycle, but it only covers what’s visible on the external bus, such as cartridge ROM/RAM and work RAM. The information suggests that during a read or write, the data is visible on the last three (for reads) or two (for writes) T-cycles of the respective M-cycle.

Unfortunately, this information is not available for the Game Boy’s video RAM and I/O registers as these reads and writes are not visible on the external bus.

Conclusion

Reliable sources on Game Boy CPU M-cycles and T-cycles are quite scarce.

The most important resource is probably Joonas Javanainen’s Game Boy: Complete Technical Reference, which provides sufficient information on CPU instruction M-cycles to effectively emulate most edge cases.

Post Updates

  • February 4, 2023: revised complete Post